Design Verification Engineer
Design Verification Engineer
scaledge technology4-6 Years
- Posted 2 days ago
- Be among the first 10 applicants
Job Description
4+Years Strong experience in System Verilog and UVM methodology
Hands-on expertise in high-speed interface protocols (PCIe / USB / DDR / Ethernet / AXI, etc.)
Good understanding of verification concepts, coverage, assertions, and debugging
Experience with simulation tools (VCS, Questa, Xcelium, etc.)
Strong analytical & problem-solving skills
More Info
Key Skills
About Company
Skills:
Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog
Skills:
C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND
Skills:
Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification
Early Applicant
Skills:
Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim
Skills:
simvision , Tcl Scripting, Vcs, Pcie, Verdi, Xcelium, Uvm, systemverilog, APB, Questa, SVA assertion writing, AXI4, AHB, CDC verification, TLP handling