Verilog, static timing analysis, Modelsim, Questa, Intel Quartus, synchronous design principles, Xilinx Vivado, RTL design methodologies, DO-254 design assurance process, Microsemi Libero, FPGA design flows, VHDL, Synthesis, timing closure techniques, FPGA design and development

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, Synthesis, Debug, test benches, Simulation, Rtl Design, Timing Closure, UVM verification flow, Verification

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4

memory controllers , Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, Libero, Unix Systems, Otn, Uvm, Microsemi FPGAs, systemverilog, Ethernet-based protocols, Axi, quartus, VHDL, scripting tools, Vivado, VMM

Pcie, Verilog, JESD204B, Isp, SERDES, Intel Quartus, systemverilog, Xilinx Vivado, Synthesis, VHDL, FFT, Video Processing Pipelines, MIPI Interfaces, CORDIC Algorithms, FIR Filters