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FPGA Design Engineer
akkodis

FPGA Design Engineer

akkodis
3-6 Years
Not Disclosed
Early Applicant
  • Posted 21 days ago
  • Be among the first 10 applicants

Job Description

Exp: 3- 6 years

Location: Bangalore

Notice Period: Immediate to 30 days

Description of the Role:

Requirement for a qualified FPGA Firmware Engineer to perform Design and Development activities. The engineer will work on various project requirements and provide technical support to meet critical delivery timelines and achieve project milestones.

Skillset Required:

Proficient in FPGA design and development using VHDL/Verilog as RTL languages.

Strong understanding of RTL design methodologies, synchronous design principles, and timing closure techniques.

Hands-on experience with FPGA design flows including synthesis, place & route, and static timing analysis.

Experience with leading FPGA toolchains such as Microsemi Libero, Xilinx Vivado, Intel Quartus, or similar.

Good understanding of simulation and debugging using ModelSim/Questa or equivalent tools.

Experience with DO-254 design assurance process is a plus.

Experience in the Activities Below:

• RTL design and development of FPGA modules from requirements and specifications.

• Micro-architecture definition and detailed design documentation.

• Constraint development (SDC/XDC), timing analysis, and timing closure.

• Functional simulation and RTL debugging.

• Integration of IP cores and third-party components into FPGA design.

• Requirement analysis, requirement review, and design review participation.

• FPGA resource utilization optimization (LUTs, FFs, BRAM, DSP).

• Hardware bring-up, board-level debugging, and lab validation support.

• Collaboration with verification, system, and hardware teams for system-level integration.

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Engineering
Employment Type:
Full time

Key Skills

Modelsim
Questa

Intel Quartus

synchronous design principles

Xilinx Vivado

RTL design methodologies

DO-254 design assurance process

Microsemi Libero

FPGA design flows

VHDL
Synthesis

timing closure techniques

FPGA design and development

Verilog
static timing analysis

About Company

Last Updated: 14-09-2026 10:24:36 PM

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