FPGA Design Engineer
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Job Description
FPGA Design Engineer Job Description
Experience Require-5-12 Y
Location-Bangalore/Hyderabad
Responsibilities:
* Design and implement FPGA solutions.
* Participate in architecture definition, implementation, and verification phases.
* Develop detailed design specifications.
* Develop and implement block-level RTL, perform synthesis, and achieve timing closure.
* Collaborate with multi-functional teams including hardware, software, diagnostics, and signal integrity groups.
* Assist in complex subsystem-level lab bring-up, integration, and unit test validation.
Required Skills and Experience
:* Experience with Xilinx, Altera, and Microsemi FPGAs
.* Proficiency in HDL languages: Verilog, VHDL, and SystemVerilog
.* Hands-on experience with FPGA vendor tools such as Vivado, Quartus, and Libero
.* Practical knowledge of Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc
.* Familiarity with simulation flows like UVM and VMM is an added advantage
.* Basic knowledge of Unix systems and scripting tools
.* 5-12 years of relevant FPGA design experience
.
Job ID: 149073295
Skills:
Simulation, FPGA development, LabVIEW FPGA, RFSoC, Rtl Design, hardware debugging, VHDL programming, Vivado, Timing Closure, Intel Altera, Modelsim, Xilinx
Skills:
hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation
Skills:
Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing
Skills:
Tcl, Verilog, Python, Perl, VHDL, systemverilog, Vivado, quartus
Skills:
Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations
