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Job Description
FPGA Design Engineer Job Description
Responsibilities:
* Design and implement FPGA solutions.
* Participate in architecture definition, implementation, and verification phases.
* Develop detailed design specifications.
* Develop and implement block-level RTL, perform synthesis, and achieve timing closure.
* Collaborate with multi-functional teams including hardware, software, diagnostics, and signal integrity groups.
* Assist in complex subsystem-level lab bring-up, integration, and unit test validation.
Required Skills and Experience
:* Experience with Xilinx, Altera, and Microsemi FPGAs
.* Proficiency in HDL languages: Verilog, VHDL, and SystemVerilog
.* Hands-on experience with FPGA vendor tools such as Vivado, Quartus, and Libero
.* Practical knowledge of Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc
.* Familiarity with simulation flows like UVM and VMM is an added advantage
.* Basic knowledge of Unix systems and scripting tools
.* 5-8 years of relevant FPGA design experience
.Job ID: 149073295
Skills:
FPGA Design, Verilog, systemverilog, Xilinx Vivado, altera quartus, Peripheral Protocols
Skills:
Fast Fourier Transform, Verilog, Digital Signal Processing, System Verilog, complex algebra, OFDM, FPGA development, Xilinx FPGA architectures, AXI4 Stream, Rtl Design, Vivado, baseband processing, AXI4 Lite, linear algebra
Skills:
hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation
Skills:
code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage
Skills:
Fpga, Algorithm Development, VLSI CAD software, Statistical Techniques, VLSI architecture, RTL design using Verilog, systemverilog, Xilinx Vivado
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