hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

Fast Fourier Transform, Digital Signal Processing, Verilog, System Verilog, Xilinx FPGA architectures, FPGA development, OFDM, complex algebra, Vivado, Rtl Design, linear algebra, AXI4 Lite, AXI4 Stream, baseband processing

memory controllers , Spi, Uart, Verilog, I2c, Pcie, Hdl Languages, Libero, Unix Systems, Uvm, Otn, systemverilog, Microsemi FPGAs, Ethernet-based protocols, Vivado, quartus, scripting tools, VHDL, VMM, Axi

Tcl, Verilog, Python, Perl, VHDL, systemverilog, Vivado, quartus

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations