FPGA Design Engineer

Verilog, MATLAB, Xilinx FPGA tools, VHDL, digital hardware circuitry, FPGA development, Simulink, measurement and debugging tools

Verilog, FPGA Design, Intel Altera Quartus, VHDL, FPGA debugging, Libero SoC, Oscilloscopes, AMD Vivado, logic analyzers

Vcs, Pcie, Verilog, Debugging, Python, Scripting, Bash, Digital Logic Design, FPGA Design, Ethernet, Tcl, high-speed interfaces, Xcelium, Simulation Tools, FPGA synthesis, LPDDR4, Altera Quartus Prime Pro, LPDDR5, systemverilog, Axi, Timing Closure, Questa, CXL, DDR5, DDR4

Spi, Pcie, Perl, Verilog, Ethernet, I2c, Python, Tcl, hardware-software integration, Otn, IP integration, systemverilog, transport system design, quartus, Vivado, MDIO, FPGA design methodologies

Tcl Scripting, Vivado Quartus or Libero Tools, RTL Design using Verilog VHDL, Hardware Debugging and Board Bring-up, FPGA Design Flow Synthesis Implementation P R Timing Closure, High-Speed Protocols PCIe Ethernet DDR Transceivers, FPGA Design and Validation, CDC Clock Domain Crossing Analysis, Simulation using Questasim, FPGA Integration Experience, Experience using Oscilloscopes and Logic Analyzers, Static Timing Analysis STA