shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings

bandgap references , Common-centroid layout, ADC DAC-related circuits, Parasitic effects, Amplifiers, LVS, physical verification sign-off flows, ESD and latch-up considerations, TSMC process nodes, Differential Pairs, Analog Mixed-Signal Layout Design, Interdigitation, ERC, Current Mirrors, DRC, Cadence Virtuoso, Device matching techniques, LDOs

matching , shielding , Tcl, Perl, Clock Routing, Resistance and capacitance reduction, EMIR simulations, Cadence Virtuoso, signal flow, High-Speed Analog Custom layout development, Mentor, Bias and Power routing

Cadence Virtuoso, EMIR simulations, Custom layouts, Mentor

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Analog Layout, Mixed Signal