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Job ID: 144755941
Skills:
Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL
Skills:
matching , parasitic effects, Cadence Tools, IR drop, reference circuits, Calibre DRC, MXL, Quantus, EM, LVS DRC PEX EMIR verification flows, LVS, xACT, Voltus, Bandgap Oscillators, Xl, StarRC, EXL, GXL, LDOs
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
CMOS/FinFET Process Technology (28nm and below), Analog Mixed-Signal Layout, DRC/LVS/LPE Verification, Deep Submicron Effects Mitigation, ESD and Latch-Up Design, EM/IR and Power Routing Considerations
Skills:
rc extraction , Programming Skills, full-custom circuit layout verification, advanced semiconductor technology, physical verification tools, EMIR analysis, mixed signal analog high speed layout, Cadence Virtuoso, Circuit Design, device physics
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