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Position: Analog Layout Engineer
Location: Hyderabad, India
Experience: 3+ Years
Job Requirements:
Responsibilities:
Mandatory Skill:
If you're planning to post this for hiring, I can also make it recruiter-ready with preferred nodes (e.g., TSMC 28nm/16nm/12nm/7nm) and specific analog IP requirements.
Interested please share your resume to [Confidential Information]
Job ID: 150896301
Skills:
shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings
Skills:
post-layout simulation, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout
Skills:
matching , shielding , Tcl, Perl, Clock Routing, Resistance and capacitance reduction, EMIR simulations, Cadence Virtuoso, signal flow, High-Speed Analog Custom layout development, Mentor, Bias and Power routing
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
Cadence Virtuoso, EMIR simulations, Custom layouts, Mentor
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