Fpga, Perl, Python, object-oriented programming, RTL, emulation platforms, test plan development, Uvm, automation scripts, systemverilog

Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, Vlsi Design, design rules

Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

Debugging, Automated Test Scripts, Documentation, Design Verification, Functional Verification, Test Plan Development