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Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 7+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
Job ID: 144750917
Skills:
Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog
Skills:
Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA
Skills:
analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis
Skills:
DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog
Skills:
C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog
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