Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft Labs- Posted a month ago
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Job Description
Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 10+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
- Hands-on experience in SoC-level and IP-level verification, including VIP integration, coverage-driven verification, and debugging
- Strong proficiency in SystemVerilog/UVM testbench architecture, including assertions, scoreboarding, and functional coverage
- Experience in IP and sub-system verification, including test plan creation, execution, and review
- Solid understanding of verification methodologies, regression management, and debug flows
- Proficiency in scripting languages such as Python or Perl for automation and regression support
- Ability to collaborate effectively with design, architecture, and cross-functional teams
- Strong analytical, problem-solving, and communication skills
More Info
Job Type:
Industry:
Function:
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Key Skills
VIP integration
scoreboarding
debug flows
regression management
verification methodologies
coverage-driven verification
execution and review
testbench architecture
assertions
functional coverage
About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage