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Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 10+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
Job ID: 144750917
Skills:
Verilog, Computer Architecture, advanced stimulus generation, Uvm, coverage-driven verification, systemverilog
Skills:
Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts
Skills:
Vcs, Shell, Perl, Python, PCIe Gen5, Xcelium, Uvm, systemverilog, AMBA, Axi, APB, Questa, CXL, AHB, SVA
Skills:
Verilog, Scripting Languages, Verification Tools, Simulators, formal verification, VHDL, Uvm
We don’t charge any money for job offers
