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Senior Design Verification Engineer
Location: Bengaluru
Experience: 5–12 Years
About the Role
Join a high-performance silicon engineering team building next-generation SoCs for AI, Data Center, Networking, and Compute platforms. You will own the verification of complex IPs and SoCs, developing robust UVM environments and driving functional verification to silicon success.
What You'll Do
What We're Looking For
Preferred: AXI/AHB/APB/CHI, Python/Perl, VCS/Xcelium/Questa, Verdi, Formal or Emulation exposure.
Job ID: 151429839
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts
Skills:
Ovm, DDR, Pcie, Perl, Verilog, Ethernet, Python, System Verilog, Tcl, UCIE, Uvm, CXL
Skills:
performance verification of ASICs, assertion-based verification, Uvm, formal tools, ASIC standard interfaces, systemverilog, Design Verification, memory system architecture, verification components
Skills:
Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB
Skills:
DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim