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Job ID: 141113941
Skills:
DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim
Skills:
performance verification of ASICs, ASIC standard interfaces, verification components, formal tools, Design Verification, assertion-based verification, Uvm, systemverilog, memory system architecture
Skills:
DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet
Skills:
simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog
Skills:
Vcs, Shell, Perl, Python, PCIe Gen5, Xcelium, Uvm, systemverilog, AMBA, Axi, APB, Questa, CXL, AHB, SVA
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