rc extraction , Ecos, Perl, Tcl, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing analysis and verification, Synthesis, PNR, Physical Design, DRC, Antenna, Cross talk, formal verification, IR-EM checks, Place And Route, Timing Analysis

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools

Docker, Python, AI ML background, Optimization, SOC domain, graph algorithms, combinatorial algorithms, geometry packages such as shapely

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

fusion compiler, physical design solutions, Design Tools

rc extraction , Ecos, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing Closure, Dft, Synthesis, PNR, DRC, Physical design flow, Cross talk, Verification Tools, formal verification, IR-EM checks, Place And Route, Timing Analysis

Static Timing Analysis, routing, chip finishing, LVS, clock-tree synthesis, Dfm, Physical Verification, DRC, Floorplan design, congestion reduction techniques, Low Power implementation, hierarchical designs, parasitic extractions, sign-off requirements, Synthesis, place route flow, placement guidelines, timing optimizations