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Job ID: 145468245
Skills:
synopsys primetime , Scripting, Shell, Perl, Python, Tcl, Siemens Calibre, IR drop, Fusion Compiler, Cadence Tools, Power Reliability, ICC2, Tempus, LVS, Innovus, Physical Verification, Timing Analysis, ERC, Physical Design Tools, Synopsys Design Compiler, Genus, DRC, EM noise analysis
Skills:
routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools
Skills:
rc extraction , Ecos, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing Closure, Dft, Synthesis, PNR, DRC, Physical design flow, Cross talk, Verification Tools, formal verification, IR-EM checks, Place And Route, Timing Analysis
Skills:
redhawk , Perl, Tcl, Yaml, Sta, BaseDRC, Synthesis, CTS extraction, Fusion Compiler, Formality, LVS analysis, Timing Analysis, Place And Route, Power Efficiency techniques, primetime, Physical Verification, timing eco’s, EM fixes, DRC, ECO methodologies, ICV, Cadence Innovus flow
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