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  • Fresher (< 1 year)

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Physical Design Engineer
reyika

Physical Design Engineer

reyika
Fresher
Not Disclosed
  • Posted a month ago
  • Over 400 applicants have applied

Job Description

1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).

2. Experience on hierarchical designs and/or Low Power implementation is an advantage.

3. Experience on Synthesis, interfacing with RTL and implementation

4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques.

5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements).

6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage

More Info

Job Type:
Permanent Job
Industry:
Other
Employment Type:
Full time

Key Skills

chip finishing

LVS

clock-tree synthesis

Dfm
Physical Verification

DRC

Floorplan design

congestion reduction techniques

Low Power implementation

hierarchical designs

parasitic extractions

sign-off requirements

Synthesis

placement guidelines

place route flow

timing optimizations

Static Timing Analysis
routing

About Company

Last Updated: 15-10-2026 03:29:03 AM

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