Search Jobs
Search by job, company or skills
Search by job, company or skills
1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).
2. Experience on hierarchical designs and/or Low Power implementation is an advantage.
3. Experience on Synthesis, interfacing with RTL and implementation
4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques.
5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements).
6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage
Job ID: 141059729
Skills:
synopsys primetime , Scripting, Shell, Perl, Python, Tcl, Siemens Calibre, IR drop, Fusion Compiler, Cadence Tools, Power Reliability, ICC2, Tempus, LVS, Innovus, Physical Verification, Timing Analysis, ERC, Physical Design Tools, Synopsys Design Compiler, Genus, DRC, EM noise analysis
Skills:
rc extraction , Ecos, Perl, Tcl, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing analysis and verification, Synthesis, PNR, Physical Design, DRC, Antenna, Cross talk, formal verification, IR-EM checks, Place And Route, Timing Analysis
Skills:
routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools
Skills:
physical design methodologies, ASIC design flows, power gating, sign-off optimizations, Floorplan, deep sub-micron technology, multi-voltage domains, Circuit Design, device physics, Netlist2GDS
Skills:
Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC
We don’t charge any money for job offers
