Physical Design Engineer
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1. Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations).
2. Experience on hierarchical designs and/or Low Power implementation is an advantage.
3. Experience on Synthesis, interfacing with RTL and implementation
4. Experience on Floorplan design, including placement of hard macros, congestion reduction techniques.
5. Experience on Static Timing Analysis related activities , parasitic extractions, sign-off requirements).
6. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is an added advantage
Job ID: 141059729
Skills:
PERL, Tcl, Sta, Synthesis, CTS, Place Route, Full-chip Floor-planning, RTL2GDSII flow, ICC2, Physical Verification, Tempus, Make scripting, layout closure, timing convergence, primetime, Innovus, Physical Design, Timing Closure, high frequency design methodologies
Skills:
Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC
Skills:
Routing, Static Timing Analysis, Low Power Synthesis, Signoff, Low Power Designs, Logical Physical Aware Synthesis, High-performance digital designs, Power Signoff, Advanced low power design techniques, UPF, Custom ASIC flows, Synthesis, Physical Verification, formal verification, Placement, Clock Tree Synthesis, CPF, Floorplan
Skills:
routing, physical design flows, digital VLSI concepts, Tempus, floor-planning, Cadence Innovus, Voltus, Timing Closure, EDA Tools, Placement, Logic Synthesis, Rtl Design
Skills:
Routing, floorplanning, Power Planning, CTS, Place And Route, Placement
