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1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
3. Implementation of a project with the full Cadence tools
4. Have worked on complex Hard macros with SerDes and/or critical in timing and area
5. Having experience in Flip-Chip SoC bump Ios)
6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113016829
Skills:
Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation
Skills:
clock distribution , Clp, PERL, Tcl, low power design, Sta, PERC, Signal Integrity Analysis, LVS, LEC flow, Tape Out, IP integration, Dfm, Timing Closure, Physical Verification, Synthesis, Gds, Tk, cpf, Clock Tree Synthesis, upf, PNR, Physical Design, ERC, DRC, Floorplan
Skills:
Perl, Verilog, Python, Tcl, power analysis optimization, power gating, Simulation, clock gating, systemverilog, UPF CPF methodologies, DVFS implementation, low-power checking tools, formal verification, RTL gate-level and physical design, EDA Tools, low-power design techniques, low-power verification flows, power performance and area PPA targets, multi-voltage
Skills:
PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure
Skills:
routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Timing Analysis, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement, Cadence simulation tools
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