Physical Design Engineer
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1. Exp. in PnR of a big SoC AMS with many partitions and not only blocks level implementation
2. Involve in a project using FDSIO 22nm technology node or equivalent (not bulk technology)
3. Implementation of a project with the full Cadence tools
4. Have worked on complex Hard macros with SerDes and/or critical in timing and area
5. Having experience in Flip-Chip SoC bump Ios)
6. Have exercised all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Job ID: 113016829
Skills:
Routing, DDR design knowledge, floorplanning, Calibre, primetime, Innovus, RTL-to-GDSII implementation, Placement, EDA Tools, Genus, Tcl tool scripting, Physical Design Methodologies, MultiTap-CTS
Skills:
clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff
Skills:
redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus
Skills:
Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff
Skills:
cadence encounter , Shell, Unix, Linux, Flow automation, Python Script, SDC STA and Equivalence checking, Tapeout sign-off experience, 10nm 7nm 5nm process nodes, Synopsys ICC2 tool set, Physical Design, PnR tools like ICC2 Innovus, Skill
