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Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.
Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world.
Job DescriptionWe are looking for a motivated Physical Design Engineer to join our Renesas team who can work independently with little or no supervision. Our candidate should be able to execute physical design flow (RTL-GDSII & STA) per planned schedule, assess risk and meet all deliverables. Candidate must monitor and drive the program from initiation to tapeout, interfacing with internal and external stakeholders and achieve alignment across cross-functional teams.
Responsibilities:
Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier.
At Renesas, you can:
Are you ready to own your success and make your mark
Join Renesas. Let's Shape the Future together.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
Job ID: 148905723
Skills:
static timing analysis, PVT conditions, timing budgeting, timing rollups, Timing Analysis, timing constraint adaptation, clock network optimization, timing models
Skills:
Perl, Python, Tcl, LVS DRC violations, Timing area and power constraints, Block-level place and route, P R flow development, CAD and physical design methodologies, Clock network guidelines, Physical design verification, Logic equivalency RTL2Synthesis, Physical Design, Synthesis2APR netlist, PPA optimization
Skills:
Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm
Skills:
PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure
Skills:
hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff
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