Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL

Routing, Circuit Design, Digital Implementation System, Floor Planning, design rule checking drc, Calibre

Synopsys StarRC, R3D, DRC, Mentor Graphics Calibre, LVS, Cadence Voltus, xACT, Cadence MXL

matching , parasitic effects, Cadence Tools, IR drop, reference circuits, Calibre DRC, MXL, Quantus, EM, LVS DRC PEX EMIR verification flows, LVS, xACT, Voltus, Bandgap Oscillators, Xl, StarRC, EXL, GXL, LDOs

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Cadence Virtuoso, Synopsys IC Compiler, Parasitic Extraction, TSMC 3nm and 5nm, analog layout design

Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters