Analog layout Engineer
- Posted a month ago
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Job Description
Exp level: 2 to 5 years
Location: Bangalore
Notice Period: Immediate joiners are preffered.
Responsibilites:
- Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCs, DACs, voltage regulators) using TSMC 3nm and 5nm nodes.
- Perform design rule checks (DRC), layout versus schematic (LVS), and electrical rule checks (ERC) to ensure design compliance.
Required Skills:
- Strong experience in analog layout design at advanced nodes (TSMC 3nm and 5nm).
- Proficiency in layout tools like Cadence Virtuoso, Synopsys IC Compiler, or similar.
- Understanding of layout-dependent effects (LDE) and its impact on performance.
- Knowledge of parasitic extraction, simulation, and optimization.
- Familiarity with design for manufacturability (DFM) techniques.
Please email Resumes to [Confidential Information]
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Key Skills
Synopsys IC Compiler
TSMC 3nm
analog layout design
About Company
Skills:
Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso
Skills:
Pvs, Python, Tcl, Methodology, FinFET nodes, Floorplan to Tape-out, Reliability Effects, Layout Techniques, Scripting in SKILL, Circuit Analysis, Verification, ESD Latch-Up, LDE Reliability, Assura, Calibre, Physical Verification, Collaboration, Project Cycles, Analog RF Layout, Power Routing, Cadence Virtuoso
Skills:
post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules
Skills:
shielding , ESD latch-up prevention, Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, Matching symmetry, Guard rings