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Exp level: 2 to 5 years
Location: Bangalore
Notice Period: Immediate joiners are preffered.
Responsibilites:
Required Skills:
Please email Resumes to [Confidential Information]
Job ID: 144764651
Skills:
Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques
Skills:
Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies
Skills:
Layout Techniques, Analog Layout Design
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