Analog layout Engineer
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Exp level: 2 to 5 years
Location: Bangalore
Notice Period: Immediate joiners are preffered.
Responsibilites:
Required Skills:
Please email Resumes to [Confidential Information]
Job ID: 144764651
Skills:
Signal integrity considerations, Analog Layout Design, Parasitic Extraction, Power distribution techniques, Analog circuit design principles
Skills:
Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology
Skills:
analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, EDA Tools, DRC, Synopsys, Cadence Virtuoso, Layout Design, Siemens tools
Skills:
Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts, DRC LVS ERC and PEX, advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies
Skills:
Synopsys, analog and mixed-signal AMS design, Analog Layout, LVS, Mentor Graphics, Cadence Virtuoso, DRC, post-layout simulation
