Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

Cpu, Ethernet, Pcie, Debugging, DDR, Uvm, Assertions, SoC Integration, SV, Coverage Closure, Complex Verification Flows, RISC-V, formal verification, IP Sub-System SoC DV Testbench Development

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB