Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features

Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning

Perl, Shell scripting, Stuck at Transition ATPG, Scan Insertion, DFT Silicon bring up expertise, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features, silicon debug, Synopsys Tetramax, SOC Tape-Outs, DFTMAX

occ, compression at core level, coverage analysis, DFT architecture, Memory-BIST, no-timing simulations, ATPG pattern generation, SSN architecture, timing simulations, Scan Insertion, clock architecture

Scan Insertion, ATPG, Silicon bring-up knowledge, Tessent DFT Compiler, MBIST, LBIST

simulations , coverage analysis, Timing Simulations, Scan Insertion, MBIST Simulations, Dft, SSN ATPG