DFT Lead Engineer
DFT Lead Engineer
BitSilica- Posted a month ago
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Job Description
- 8 to 10+ yrs of experience in DFT architecture, scan Insertion, compression at core level and SoC level.
- Experience in ATPG pattern generation, coverage analysis
- Experience with timing and no-timing simulations
- Experience in Memory-BIST
- Have understanding of SSN architecture, clock architecture, OCC
More Info
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Key Skills
DFT architecture
compression at core level
no-timing simulations
Memory-BIST
ATPG pattern generation
SSN architecture
timing simulations
clock architecture
About Company
Skills:
Design for Test (DFT), Perl, Python, Tcl, Coverage Optimization, IEEE 1500 Standards, Gate-Level Simulation, Scan Insertion, Scan Architecture, MBIST Implementation, Fault Simulation, Scan Compression, ATPG Generation, DFT Validation, Scan Debug
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress
Skills:
boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis
Skills:
Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis