Lead DFT Engineer
Lead DFT Engineer
taglynk- Posted 3 hours ago
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Job Description
About the Client
Our client is a leading semiconductor and systems engineering services company.
About the Role
We are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.
Key Responsibilities
- Define and implement DFT architecture for complex SoCs and IPs.
- Drive Scan Insertion, scan compression, scan stitching, and scan verification.
- Develop and integrate MBIST solutions for embedded memories and memory repair flows.
- Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.
- Perform DFT verification, coverage analysis, pattern validation, and debug.
- Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.
- Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.
- Develop automation scripts to improve DFT productivity and flow efficiency.
Requirements
- 10–12 years of hands-on experience in Design for Test (DFT).
- Strong expertise in Scan Insertion, scan compression, and scan architecture.
- Deep experience with MBIST implementation, integration, and verification.
- Strong knowledge of ATPG generation, fault simulation, and coverage optimization.
- Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.
- Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.
- Experience with DFT validation, gate-level simulation, and scan debug.
- Proficiency in TCL, Python, or Perl scripting for flow automation.
- Excellent debugging, analytical, and cross-functional collaboration skills.
Qualifications
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, or a related discipline.
More Info
Job Type:
Industry:
Employment Type:
Key Skills
Design for Test (DFT)
Coverage Optimization
IEEE 1500 Standards
Gate-Level Simulation
Scan Architecture
MBIST Implementation
Scan Compression
ATPG Generation
DFT Validation
Scan Debug
About Company
Skills:
Perl, Shell scripting, DFT verification, Synopsys Tetramax DFTMAX, VCS simulation tool, IEEE1500, Scan memory BIST, JTAG 1149.x, Verilog RTL design, Design for Test methodologies, Mentor testkompress
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis
Skills:
boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis
Skills:
DFT architecture, occ, compression at core level, coverage analysis, no-timing simulations, Memory-BIST, ATPG pattern generation, SSN architecture, Scan Insertion, timing simulations, clock architecture