Lead DFT Engineer
Lead DFT Engineer
lancesoft, inc.8-10 Years
- Posted 9 hours ago
- Be among the first 10 applicants
Job Description
Lead DFT Engineer
Location: Bangalore
Experience: 8+ Years
Job Description
We are looking for an experienced Lead DFT Engineer with strong expertise in Design-for-Test (DFT), ATPG, and MBIST, along with hands-on experience using Cadence tools.
Key Responsibilities
- Lead DFT architecture, implementation, and verification for complex SoC designs.
- Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.
- Implement and verify MBIST, memory test architectures, and test controllers.
- Perform DFT rule checks (DRC), scan chain analysis, and test coverage optimization.
- Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
- Support DFT sign-off, test pattern validation, and production test readiness.
Must-Have Skills
- 8+ years of hands-on DFT engineering experience.
- Strong expertise in ATPG and MBIST.
- Hands-on experience with Cadence DFT tools.
- Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.
- Strong debugging, problem-solving, and cross-functional collaboration skills.
Preferred Skills
- Experience with full-chip SoC DFT implementation and silicon validation.
- Knowledge of JTAG, boundary scan, and IEEE 1500/1687 standards.
- Experience supporting DFT sign-off and manufacturing test requirements.
More Info
Key Skills
About Company
Skills:
synopsys tools , MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification
Skills:
Dft, ATPG, MBIST, CCS JTAG
Skills:
Perl Shell Scripting, Scan Insertion, Stuck at Transition ATPG, Production enablement, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, VCS simulation tool, Scan Architecture, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Post Silicon Bring Up Planning, Scan features
Skills:
Scan insertion and compression, DFT architecture planning, Boundary scan IEEE 1149.1 1149.6 IJTAG 1687, MBIST, Fault grading, ATPG pattern generation, Logic BIST insertion and validation, Synthesis flows, Rtl Design, Sta
Skills:
Perl Shell Scripting, Scan Insertion, Production enablement, Stuck at Transition ATPG, Synopsys Tetramax DFTMAX, DFT Silicon bring up expertise, Silicon Debug for Phasing closure, Yield Analysis Debug, Test cost reduction analysis, Scan Architecture, VCS simulation tool, GLS Timing and Power Aware Simulations, IDDQ Pattern Generation, Verilog RTL design, ATPG pattern generation, Mentor testkompress, Scan features, Post Silicon Bring Up Planning