Staff Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
Job Description:
Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).
Should be able to meet congestion, timing and area metrics. Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.
Should have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.
Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.
Candidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.
Should possess ability to learn and adapt to new tools and methodologies.
Excellent communication skill is a must.
R026385
Candidate would be required to work on various phases of SOC physical design activities. The job will include but not limited to block level – floor-planning, partitioning, placement, clock tree synthesis, route, physical verification (LVS/DRC/ERC/Antenna etc).
Should be able to meet congestion, timing and area metrics. Candidate would be required to do equivalence checks, STA, Crosstalk delay analysis ,noise analysis, power optimization. Should be able to implement timing and functional ECOs.
Should have excellent problem solving skill to help through congestion resolution and timing closure. Should have experience formal verification and timing analysis and ECO implementation.
Experience with tools such as Innovus/Encounter, ICC, Caliber, LEC, Primetime etc is highly desirable.
Candidate should be able to work independently and guide other team members. Should be experienced in working in a global team and dynamic environment.
Should possess ability to learn and adapt to new tools and methodologies.
Excellent communication skill is a must.
R026385
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
floor-planning
noise analysis
Innovus
equivalence checks
Encounter
ICC
DRC
timing and functional ECOs
Crosstalk delay analysis
About Company
Skills:
rtl verification , Ovm, Verilog XL, DC Ultra, cdc, GLS simulation, Memory BIST, RTL Synthesis, Fusion Compiler, MBIST, LEC, Uvm, Synthesis tools, Verilog NC, RSQ, Dft, spyglass, Verification methodologies, ATPG, ICC Synthesis constraints
Skills:
boundary scan , Jtag, Perl, Python, Tcl, LINT, ASIC design flow, DFT DRC, cdc, Analog DFT, MBIST, Scan compression, Scan stitching, Dft, Low power DFT Techniques, ATPG, Low Power Checks, RTL Coding, ATPG Coverage improvement, LBIST, DFT STA Constraint development
Skills:
Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB
Skills:
Physical Design, Physical verification and signoff checks, Timing Closure, Timing optimization and closure, floorplanning, EDA tools for physical design verification, Low-power design methodologies, Static and Dynamic IR drop analysis, Package co-design, Placement and routing, Power grid design
Skills:
clocking , power delivery , C, Version Control Systems, Python, Git, chip finishing, distributed processing, physical verification flows, advanced-node SoC physical implementation, technology PPA optimization, EDA Tools, dynamic power, Timing, memories, low-power design methodologies, Libraries, Physical Verification, debug environments, technology-node tradeoffs, routing resources, congestion, UPF-based design, implementation methodology development, scripting skills, leakage