rtl verification , Ovm, Verilog XL, DC Ultra, cdc, GLS simulation, Memory BIST, RTL Synthesis, Fusion Compiler, MBIST, LEC, Uvm, Synthesis tools, Verilog NC, RSQ, Dft, spyglass, Verification methodologies, ATPG, ICC Synthesis constraints

boundary scan , Jtag, Perl, Python, Tcl, LINT, ASIC design flow, DFT DRC, cdc, Analog DFT, MBIST, Scan compression, Scan stitching, Dft, Low power DFT Techniques, ATPG, Low Power Checks, RTL Coding, ATPG Coverage improvement, LBIST, DFT STA Constraint development

Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB

Physical Design, Physical verification and signoff checks, Timing Closure, Timing optimization and closure, floorplanning, EDA tools for physical design verification, Low-power design methodologies, Static and Dynamic IR drop analysis, Package co-design, Placement and routing, Power grid design

clocking , power delivery , C, Version Control Systems, Python, Git, chip finishing, distributed processing, physical verification flows, advanced-node SoC physical implementation, technology PPA optimization, EDA Tools, dynamic power, Timing, memories, low-power design methodologies, Libraries, Physical Verification, debug environments, technology-node tradeoffs, routing resources, congestion, UPF-based design, implementation methodology development, scripting skills, leakage