Staff Engineer
Staff Engineer
BroadcomFresher
- Posted 21 hours ago
- Be among the first 10 applicants
Job Description
Job Description:
Broadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is a great opportunity and challenging role for the people who want to gain in-depth knowledge on end to end chip development flow with deeper expertise on RTL, Synth and Memory BIST
Responsibilities
Broadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is a great opportunity and challenging role for the people who want to gain in-depth knowledge on end to end chip development flow with deeper expertise on RTL, Synth and Memory BIST
Responsibilities
- RTL development and Verification for Digital subsystems, Memory Subsystems including BIST.
- Memory Digital Subsystems with Tessent/Embedded MBIST
- MBIST, ATPG, RSQ Verification and sign-off.
- Formal verification, Cross Clock Domain checks, Power/Timing sign off
- Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently.
- Hands on Experience with RTL, Synthesis,
- Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs
- Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the DFT signoff.
- Familiarity with Spyglass, LEC, CDC, and Synthesis tools DC Ultra, Fusion Compiler.
- Familiarity with GLS, simulation, UVM, OVM methodologies is a big plus
- Proficiency with Verilog NC, Verilog XL tools
- Strong fundamentals in digital design and Coding/Verifying complex RTL subsystems
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
DC Ultra
GLS simulation
Memory BIST
RTL Synthesis
Fusion Compiler
Synthesis tools
Verilog NC
RSQ
Verification methodologies
ICC Synthesis constraints
About Company
Skills:
Digital Logic Design, Scripting, LINT, cdc, Processor SoC architecture, formal equivalence, Post Silicon issue debug, ASIC tapeouts, DSP fundamentals, ECO flows
Skills:
bist , Test Execution, Functional Testing, Perl, Scripting Languages, Python, Tcl, Scan Insertion, digital design concepts, ATPG, test plan development, EDA Tools, MBIST implementation, Cadence, Mentor, Synopsys
Skills:
Verilog, Microprocessors, Usb, Logic Design, Pcie, LINT, cdc, pad ring, SoC clocking, Design Compiler, Asynchronous interface, Synthesis, SDCC, RTL Coding, micro-architecture, Low power SoC design, System-Verilog, constraint development, SOC design, chip level floorplan, Memory controller designs, reset debug architecture, AMBA protocols, primetime, Axi, APB, timing concepts for ASIC, Timing Closure, Multi Clock designs, AHB
Skills:
caliber , power optimization , Sta, floor-planning, LVS, noise analysis, Innovus, Antenna, equivalence checks, Encounter, LEC, ICC, Physical Verification, primetime, ERC, DRC, partitioning, Placement, timing and functional ECOs, Crosstalk delay analysis, Clock Tree Synthesis
Skills:
System Verilog, Digital-analog interface requirements, RTL design and development, Linting, Mixed-signal design flows, RDC analysis, Coverage-driven design methodologies, Timing Constraints, Digital control logic, Synthesis and timing closure methodologies, RTL coding in Verilog, Low-power design techniques