STA Engineer
STA Engineer
leadsoc technologies pvt ltd- Posted 20 hours ago
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Job Description
We're Hiring | STA Engineer | 5+ Years
LeadSoc Technologies Pvt. Ltd. is looking for experienced Static Timing Analysis (STA) Engineers to join our VLSI team in Bangalore.
Position: STA Engineer
Experience: 5+ Years
Location: Bangalore
Notice Period: 0–Immediate Joiners Preferred
Key Responsibilities
- Perform block-level and full-chip Static Timing Analysis (STA)
- Analyze and resolve setup and hold timing violations
- Develop, validate, and debug SDC timing constraints
- Perform MMMC/PVT timing analysis and closure
- Work on clock and timing-path analysis
- Support timing ECOs and optimization
- Collaborate with Physical Design, Synthesis, and Signoff teams
- Debug complex timing issues and drive timing closure
- Support timing signoff activities
Required Skills
- Strong hands-on experience in STA and Timing Closure
- Good knowledge of SDC constraints
- Expertise in Setup/Hold analysis
- Experience with PrimeTime / Tempus
- Knowledge of MMMC, PVT, OCV/AOCV/POCV
- Understanding of CTS, clock analysis, and Physical Design flow
- Scripting knowledge in Tcl / Perl / Python is an advantage
- Experience with ECO implementation and timing optimization
Education
- B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical Engineering (EEE), VLSI, or a related field
- Strong academic background with relevant VLSI/ASIC design knowledge preferred.
Preferred Profile
Candidates with strong experience in full-chip/block-level STA, timing debug, constraint development, and signoff closure are preferred.
Interested candidates can share their updated resume at:
[Confidential Information]
More Info
Key Skills
About Company
Skills:
QRC, primetime, STA and signoff tools, Tempus
Skills:
synopsys primetime , Perl, Static Timing Analysis, Python, Tcl, Timing exceptions, OCV, ASIC implementation, Full-chip STA, Timing sign-off, Timing Closure, SDC, MMMC, POCV, Si, Physical design flow, AOCV
Skills:
Clp, automation, Scripting, LINT, prelayout STA, low power aspects, postlayout STA, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking
Skills:
RTL synthesis, setup hold analysis, advanced SoC design flows, Timing Closure, SDC constraints development, PPA optimization, Cadence Genus
Skills:
synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff