Lead Synthesis & STA Engineer
Lead Synthesis & STA Engineer
lancesoft, inc.- Posted 15 hours ago
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Job Description
Title: Lead Synthesis & STA Engineer
Location: Bangalore
Experience: 8+ Years
Job Description
We are looking for an experienced Lead Synthesis & STA Engineer with strong expertise in RTL synthesis, full-chip Static Timing Analysis (STA), and Cadence EDA tools.
Key Responsibilities
- Lead RTL synthesis, timing analysis, and optimization for complex SoC designs.
- Perform full-chip STA, timing closure, and setup/hold violation analysis.
- Drive timing, power, and area (PPA) optimization.
- Work on SDC constraints development, validation, and timing exceptions.
- Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
- Lead design reviews, debug critical paths, and drive closure activities.
Must-Have Skills
- 8+ years of experience in RTL Synthesis and Static Timing Analysis.
- Strong hands-on experience with Cadence Genus and Tempus.
- Expertise in full-chip STA, timing constraints, and timing closure.
- Strong knowledge of SDC, setup/hold analysis, and timing optimization.
- Experience with PPA optimization and advanced SoC design flows.
More Info
Key Skills
RTL synthesis
setup hold analysis
advanced SoC design flows
SDC constraints development
PPA optimization
Cadence Genus
About Company
Skills:
synopsys primetime , Static Timing Analysis, Perl, Python, Tcl, SDC constraints, RTL Synthesis, STA timing constraints, ASIC SoC implementation and signoff methodologies, Synopsys Design Compiler, ECOs and timing fixes, critical path analysis, implementation flows, RTL-to-gate synthesis, Fusion Compiler, setup hold analysis, Timing Closure, timing optimization