QRC, primetime, STA and signoff tools, Tempus

synopsys primetime , Perl, Static Timing Analysis, Python, Tcl, Timing exceptions, OCV, ASIC implementation, Full-chip STA, Timing sign-off, Timing Closure, SDC, MMMC, POCV, Si, Physical design flow, AOCV

Clp, automation, Scripting, LINT, prelayout STA, low power aspects, postlayout STA, Synthesis, cdc, SDC generation, demotion, SDC development, LEC, RTL Netlist based static checks, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking

RTL synthesis, setup hold analysis, advanced SoC design flows, Timing Closure, SDC constraints development, PPA optimization, Cadence Genus

synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, RTL to GDS, primetime, Innovous, ASIC back-end design flows, STA setup, Timing Analysis

Scripting, Clp, Automation, LINT, cdc, Prelayout STA, SDC generation, SDC development, LEC, Low power aspects, RTL Netlist based static checks, Timing Closure, Synthesis, Postlayout STA, Timing Constraints

synopsys primetime , Tcl, Python, Perl, ECO Implementation, Cadence Tempus, Constraint Management, Signal Integrity

Clp, automation, Scripting, LINT, cdc, SDC generation, SDC development, LEC, RTL Netlist based static checks, prelayout STA, low power aspects, postlayout STA, Synthesis, demotion, Dft, Timing Constraints, Timing Closure, Verification, promotion, equivalence checking