Lead STA Engineer
Lead STA Engineer
leadsoc technologies pvt ltd- Posted 4 hours ago
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Job Description
Lead STA Engineer
Location: Bengaluru
Experience: 6–12 Years
Role Overview
We are looking for a Lead STA Engineer with strong hands-on expertise in Static Timing Analysis and timing closure for complex ASIC/SoC designs.
Key Responsibilities
- Own full-chip/block-level STA across multiple modes and corners.
- Perform setup/hold analysis, timing closure and ECO implementation.
- Develop and validate SDC constraints, clock definitions and timing exceptions.
- Analyze MMMC, OCV/AOCV/POCV, SI and clock-related timing issues.
- Drive timing correlation across Synthesis, P&R and sign-off.
- Debug and resolve setup, hold, max transition, max capacitance and constraint violations.
- Work closely with RTL, Synthesis, Physical Design and DFT teams for timing closure.
- Drive PPA and timing optimization for high-performance SoCs.
- Develop/debug STA flows and automation using Tcl/Python/Perl.
- Support sign-off, tape-out and critical timing closure activities.
Required Skills
- 6–12 years of relevant STA experience.
- Strong hands-on expertise in Synopsys PrimeTime or equivalent STA tools.
- Strong understanding of SDC, MMMC, clocking, timing exceptions and STA fundamentals.
- Experience with OCV/AOCV/POCV, SI and advanced-node designs.
- Good understanding of ASIC implementation and physical design flow.
- Strong scripting skills in Tcl/Python/Perl.
- Experience in full-chip STA and timing sign-off preferred.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Timing exceptions
ASIC implementation
Full-chip STA
Timing sign-off
MMMC
POCV
Physical design flow
AOCV
About Company
Skills:
synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff
Skills:
Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus
Skills:
synopsys primetime , Perl scripting, Static Timing Analysis, SDC constraints, RTL Synthesis, STA timing constraints, mmc, Timing optimization, Critical path analysis, ASIC SoC implementation and signoff methodologies, Setup hold analysis, Timing Closure, MCMM, Synopsys Design Compiler, ECOs and timing fixes
Skills:
synopsys primetime , Perl, Shell scripting, Python, Tcl
Skills:
STA Engineer, Timing Lead, primetime, PT-DMSA, OCV/AOCV/POCV, Signal Integrity, TCL scripting skills, Tempus, ECO generation, PNR