Senior Design Verification Engineer

Design Verification

Exp- 5 to 12 Yrs

Location- Hyderabad/Bangalore

NP- 0 to 30 days max

Oversees definition, design, verification, and documentation for ASIC development.

Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Must Have:

1). Strong hands-on experience on UVM with creating TB components like Driver, Monitor & Scoreboard

2). Should be strong in Verilog concepts, UVM, Verilog, DDR or any PHY verification

3). Candidate should have strong knowledge on what is included in Resume.

4). Good to have prior experience in DDR or any PHY verification

Interested candidates can share resume to [Confidential Information]