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Scaledge Technology

Senior Design Verification Engineer

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  • Posted 9 days ago
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Job Description


We're Hiring | Senior Design Verification Engineer

Are you a Senior Design Verification Engineer with strong hands-on experience in SystemVerilog & UVM

Join us to work on cutting-edge silicon and build scalable, high-performance solutions.

Role: Senior Design Verification Engineer

Experience: 5+ Years

Locations: Bangalore | Hyderabad | Noida | Pune | Ahmedabad

Key Requirements:

  • 5+ years of experience in Design Verification
  • Strong hands-on experience with SystemVerilog & UVM
  • Expertise in functional coverage and SystemVerilog assertions
  • Exposure to protocols like AXI / PCIe / USB / DDR
  • Excellent debugging, problem-solving, and collaboration skills

What you will do:

  • Develop and maintain UVM-based verification environments
  • Create test plans, coverage models, and assertions
  • Debug complex RTL and verification issues
  • Collaborate closely with design and architecture teams

Apply / Refer: Share your resume at [Confidential Information]

Let's build scalable and high-performance silicon together!

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Job ID: 142648771

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