Senior Design Verification Engineer
Senior Design Verification Engineer
systechcorp inc- Posted a day ago
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Job Description
Hiring: Design & Verification Engineer
Location: Hyderabad
Interview: Mandatory in-person interview
We are looking for experienced Design & Verification professionals with strong expertise in PCIe, UVM, SystemVerilog, NAND and DDR verification.
Required Skills- 5–10+ years of relevant industry experience
- Strong IP / Block / Subsystem / SoC verification experience
- Expert-level SystemVerilog & UVM
- Strong PCIe IP / Subsystem verification experience
- Experience with NAND, DDR and PCIe
- AXI/AHB protocol experience
- Experience creating block-level, subsystem and SoC test plans
- Strong knowledge of verification methodologies, flows and quality metrics
- Hands-on experience with ASIC simulation tools
- Excellent debugging and problem-solving skills
- Perl/Python scripting is an added advantage
Education: B.S. in Electrical Engineering, Computer Science, or equivalent industry experience.
Interested candidates can send their updated resumes to:
[Confidential Information]
More Info
About Company
Skills:
Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification
Skills:
Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog
Skills:
C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification
Skills:
Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions
Skills:
Usb, Nvme, DDR, Shell, Perl, Pcie, Verilog, Ethernet, Python, System Verilog, Tcl, UPF Low Power Verification, CHI, Linux development environments, Uvm, formal verification, ASIC design flows, Axi, CXL, NLP Testbench Verification, System Verilog Assertions