Senior Design Verification Engineer
Senior Design Verification Engineer
einfochips (an arrow company)5-7 Years
- Posted 6 hours ago
- Be among the first 10 applicants
Job Description
We are hiring experienced ASIC Verification Engineers with strong hands‑on expertise in SystemVerilog, UVM, and IP/SOC verification. The role involves leading a small team, defining testbench architecture, developing UVM environments, and driving coverage closure. Experience with debug tools (IUS/VCS/Questa/Verdi), scripting (Python/Perl/Shell), and protocols like AXI, PCIe, DDR, USB, CXL, Ethernet, etc., is highly preferred. Knowledge of CPU-based verification, NoC, low‑power/GLS is a plus. Strong ownership and communication skills are essential.
Experience: 5+ years
Location: Hyderabad/Bangalore/Noida/Ahmedabad/Pune/Chennai
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Key Skills
About Company
Skills:
Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog
Skills:
C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification
Skills:
Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
Skills:
simvision , Perl, Python, PrimeSim, FineSim, Hspice, Test Vectors, Xcelium, WaveView, Analog Spice Simulation, Test Benches, SpectreFx, Verification Methodology, virtuoso, SV UVM, FastSpice