Senior Design Verification Engineer
Senior Design Verification Engineer
Smart Soc SolutionsThis job is no longer accepting applications
Job Description
SmartSoC Solutions is looking for Design Verification Engineer to join our dynamic team and embark on a rewarding career journey.
- Developing and executing test plans and procedures to verify the functionality and performance of a design
- Identifying and documenting design defects and issues, and working with designers and other stakeholders to address them
- Analyzing test results and data to identify patterns and trends, and making recommendations for design improvements
- Developing and implementing automated test scripts and test frameworks to improve testing efficiency and accuracy
- Collaborating with other engineers and stakeholders to ensure that all design requirements are properly verified and validated
- Creating and maintaining documentation related to the verification and validation process, including test plans, test reports, and traceability matrices
- Participating in design reviews and providing feedback on design requirements and testability
- Providing technical support and expertise to other departments, to ensure that designs are implemented correctly and meet all necessary requirements
- Strong analytical and problem-solving skills, with the ability to identify areas for improvement and develop effective solutions.
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Key Skills
About Company
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end Semiconductor, Embedded, Automotive and System Design to design and build next-generation leadership products under one roof. And allowing clients to achieve both quick wins and long-term results.
Our goal is to be an extended arm of engineering product and IT companies and ensure good quality productization cost-effectively.
Skills:
Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA
Skills:
Design Verification, Debugging RTL Verilog designs
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
Perl, Debugging, Test Plan Creation, Python, VIP integration, scoreboarding, debug flows, regression management, verification methodologies, Uvm, coverage-driven verification, execution and review, systemverilog, testbench architecture, assertions, functional coverage
Skills:
Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, UVM methodology, Coverage-driven verification, systemverilog, Functional Verification