Search by job, company or skills

Senior Design Verification Engineer

Senior Design Verification Engineer

BitSilica
5-7 Years
Not Disclosed
Early Applicant
  • Posted 2 months ago
  • Be among the first 10 applicants

Job Description

•5 Years of ASIC SoC Verification Experience

• Expertise in SV-UVM, C, Assertions coding

• Must have good understanding of ARM processor based SoC architecture and must have completed verification of two or more embedded processor based SoC

• Must have expertise in on ASIC verification methodologies and ASIC design flow.

• Have expertise on ARM based SOC software framework (multi-core multi-layer APIs)

• Proven experience of the design verification methodologies such as UVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation

• Strong problem solving/debugging skills

• Experience on working in SOC with complex Analog-Digital Interface will be considered as advantage.

• Experience on working in SOC with WREAL/AMS model will be considered as advantage

• Experience in Scripting Languages like Perl, awk, sed, will be an advantage

More Info

Job Type:
Industry:
Employment Type:

Key Skills

ASIC design flow

C Assertions coding

ARM based SOC software framework

Analog-Digital Interface

WREAL AMS model

SV-UVM

UVM assertion based coverage driven verification

constraint random test generation

multi-core multi-layer APIs

functional coverage

ARM processor based SoC architecture

ASIC verification methodologies

About Company

Similar Jobs

6-8 yrs
Bengaluru, India
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
6-10 yrs
Bengaluru, India
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
5-7 yrs
Bengaluru, India
Skills:
Vcs, Shell, Perl, Python, Verdi, Assertions SVA, Verification planning, RISC-V, Regression and debug, UVM testbenches, Uvm, systemverilog, Test-plan development, Functional and code coverage, DDR verification, Questa
5-7 yrs
Bengaluru, India
Skills:
Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping
5-7 yrs
Bengaluru, India
Skills:
Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation