Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

Design Verification, Debugging RTL Verilog designs

Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage

Perl, Debugging, Test Plan Creation, Python, VIP integration, scoreboarding, debug flows, regression management, verification methodologies, Uvm, coverage-driven verification, execution and review, systemverilog, testbench architecture, assertions, functional coverage

Shell, Perl, Python, Tcl, Debugging RTL verification issues, Assertions SVA, UVM methodology, Coverage-driven verification, systemverilog, Functional Verification

Git, C, Bug Tracking Tool, System Verilog, Models for performance verification, Performance test plan development, Cadence, RTL simulations, Monitors, Synopsys, Transactors

ASIC design flow, C Assertions coding, ARM based SOC software framework, Analog-Digital Interface, WREAL AMS model, SV-UVM, UVM assertion based coverage driven verification, constraint random test generation, multi-core multi-layer APIs, functional coverage, ARM processor based SoC architecture, ASIC verification methodologies