Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework

Tcl, Python, Perl, systemverilog, Functional Verification, UVM methodology, High-speed networking interfaces, Coverage-driven verification, Ethernet IPs, Emulation platforms or FPGA prototyping

Integrated circuitry, Design Verification, Software simulations, Analog and mixed signal electronic parts

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations

Verilog, random stimulus, VMM, assertion-based verification, Uvm, systemverilog, functional coverage, advanced verification methodologies