Senior Design Verification Engineer

Project Description:

We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.

At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way.

Responsibilities:

* Responsible for creating a test bench for the client IP.

* Responsible for running simulation and coverage metrics for client IP

* Responsible for creating PL designs using Vivado and Vitis.

* Responsible for creating Regressions using Python scripts

Mandatory Skills Description:

* Strong proficiency in SystemVerilog and verification methodologies (UVM preferred) with 4-8 yrs experience

* Hands-on experience with QuestaSim and/or Synopsys VCS simulation environments.

* Proven experience creating testbenches, constrained-random tests, scoreboards and coverage models.

* Solid understanding of functional coverage and code coverage metrics and how to drive closure.

* Good RTL understanding (Verilog/VHDL) and ability to read and debug design source.

* A good knowledge of simulation flow

* Working experience with Vivado project flows.

* Working knowledge of Xilinx/AMD devices.

* Working experience with Linux environment.

Nice-to-Have Skills Description:

* Working experience on any scripting language (TCL/Shell/Python).

* Good to have experience in Vitis flows.