Senior Design Verification Engineer

Senior Design Verification Engineer

Experience : 4 years

Location : Hyderabad

Job Description:Strong proficiency in SystemVerilog and verification methodologies (UVM preferred).

Hands-on experience with QuestaSim and/or Synopsys VCS simulation environments.

Proven experience creating testbenches, constrained-random tests, scoreboards and coverage models.

Solid understanding of functional coverage and code coverage metrics and how to drive closure.

Good RTL understanding (Verilog/VHDL) and ability to read and debug design source.

A good knowledge of simulation flow

Working experience on Vivado project flows.

Working knowledge on Xilinx/AMD devices.

Working experience on Linux environment.

Working experience on any scripting language (TCL/Shell/Python).

Good to have experience in Vitis flows.

Interested,please share your updated resume to [Confidential Information]