Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification

Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

rtl verification , Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench, SystemVerilog PLI coding

arm architecture , C, Usb, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

arm architecture , Usb, C, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM

Usb, Tcp Ip, Windows, Pcie, Linux, Ethernet, C Programming, RTL design and development, Test generators, HW testing, UVM testbenches, FPGA Verilog design, Packet processing, Debugging RTL code, Traffic analyzers

C, Requirements Traceability, Test Plan Creation, Tcl, Verilog, System Verilog, Python, Perl, Microprocessor architecture, interconnect, Assertions, UVM methodology, Gate Level Simulation, Testcase creation, Directed and constrained random methodologies, Metric Driven Verification, Coverage closure, Formal verification methodologies, SoC Verification, Functional and code coverage