Senior Design Verification Engineer
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Job Location: Hyderabad
Notice Period: 15 days to 30 Days
Minimum: 4 Years
Key Responsibilities:
Preferred Experience:
Should have worked on Processor based System or Sub-system level verification
Hands on experience with assembly, UVM, SV, C++
Experience in developing complex test bench/model in UVM, Verilog, System Verilog
Hands on experience in developing test plans, coverage closure
Ability to code readable, maintainable and verifiable code using UVM, SV, Strong digital design concepts
Experience in developing asm/C++ tests will be an added advantage
Experience in Power Management, Clock, Reset will be an added advantage
Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage
Job ID: 144847745
Skills:
Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Scripting, Verdi, IUS, Uvm, GLS, systemverilog, debug tools, Axi, IP SOC verification, Questa, CXL, CPU-based verification
Skills:
Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth
Skills:
Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
Skills:
arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support
