RTL Design Engineer, Core-IP

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
• 3 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
• Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP)
• Experience with a scripting language such as Perl or Python

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science
• 6 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
• Experience in area, power and performance design optimization
• Experience in design and development of security or audio blocks

Responsibilities

• Collaborate with architects and develop microarchitecture.
• Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks.
• Develop RTL implementations that meet competitive power, performance and area targets.
• Participate in synthesis, timing/power closure, and support pre-silicon and post-silicon bring-up.
• Participate in test planning and coverage analysis. Create tools/scripts to automate tasks and track progress.