Verilog, LINT, cdc, Micro-architecture development, Functional Safety concepts, systemverilog, Synthesis checks, RDC, ASIL requirements, RTL design and integration, ISO 26262, Safety analysis methodologies

Verilog, Sta, Synthesis, cdc, Dft, ATPG, RTL Coding, LINT, SDC creation, systemverilog

Pcie, Verilog, Ethernet, Debugging, Scripting, Python, Tcl, UCIe chiplet interconnects, digital design fundamentals, high-speed IO protocols, systemverilog, Rtl Design, CXL, micro-architecture, low-power design techniques

Perl, Verilog, Python, Synthesis, processor design, low power design techniques, arithmetic units, Chisel, memory hierarchies, design for testing, timing power analysis, systemverilog, Asic Design Verification, accelerators, micro-architecture, bus architectures

CDC RDC closure, spyglass, RTL refactoring, Formal verification methods, Integration testplans, Synthesis flows, ASIC RTL design

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Tcl, Python, Perl, Ace, systemverilog, CHI, cdc, debugging functional and performance issues, Verilog RTL development, performance optimization, LINT, Synthesis, Resets, RDC, AMBA protocols