RTL Design Engineer
RTL Design Engineer
ALTEN Calsoft Labs- Posted 6 months ago
- Be among the first 10 applicants
Job Description
Job Title: RTL Design Engineers
Exp Level: 4+ yrs
Loctaion: Hyderabad /Bangalore
Job Description:
• RTL coding knowledge
• Top-level (SOC) level basic industry standard Arch knowledge
• SoC & IP level Integration knowledge
• IPXACT knowledge
• IORING and Phys & GPIOs basic functionality
• Design Partitioning(Tilification) knowledge
• Design RTL quality checks:
- Clock domain crossing(CDC)
- Reset domain crossing(RDC)
- LINT
- VSI
- UPF knowledge
- LEC(Logic equivalence check)
- Timing concepts & SDC knowledge
• Tools knowledge:
- Vc_static or equivalent other tools(VSI)
- VC_spyglass LINT, CDC and RDC
- 0in
- Formality and conformal LEC tool
• Design and scripting languages:
- Verilog and SV
- Perl
- Python
- TCL
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
VC spyglass
IPXACT
Formality
VSI
UPF
0in
IORING
SoC IP level integration
Design Partitioning
About Company
Skills:
Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms
Skills:
Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design
Early Applicant
Skills:
Verilog, systemverilog, DDR memory controller calibration, Rtl Design, Logic analyzers, Calibration algorithms
Skills:
Python Scripting, RTL design in Verilog SystemVerilog, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, PrimeTime or equivalent tools, C embedded experience, Circuit timing STA
Skills:
Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, FPGA design flow, Timing Closure, 5G LTE, Altera Agilex