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198

Lint Jobs

CPU Logic Design Engineer

Permanent Job

Bengaluru / Bangalore ,

5-7 years

power management cdc Static tools (UPF Digital Design Principles Verilog/System Verilog language Execution Unit x86 Core processor architecture LINT memory features RDC) Integration Cache

6 days ago

CPU Logic Design Engineer

Permanent Job

Bengaluru / Bangalore ,

5-7 years

power management cdc Static tools (UPF Digital Design Principles Verilog/System Verilog language Execution Unit x86 Core processor architecture LINT memory features RDC) Integration Cache

6 days ago

CPU Logic Design Engineer

Permanent Job

Bengaluru / Bangalore ,

3-5 years

power management cdc UPF Digital Design Principles Execution Unit x86 Core processor architecture RDC LINT memory features Verilog Integration Cache System Verilog

6 days ago

SoC RTL Design Engineer

Permanent Job

Bengaluru / Bangalore ,

8-11 years

ASIC SoC clocking Synthesis System-Verilogis primetime ASIC development RTL Coding Tools Motivated AHB constraint development Memory controller designs Oral APB Axi Low power SoC design Creative reset Asynchronous interface LINT Design Compiler Multi Clock designs Timing Concepts Curious cdc written communications skills SOC design Proactive micro-architecture debug architecture chip level floorplan team collaboration skills Timing Closure padring SDCC AMBA protocols Usb Verilog Pcie Peripherals Logic Design Microprocessors

3 days ago

ASIC Design -Staff / Camera

Permanent Job

Bengaluru / Bangalore ,

3-5 years

ASIC clock domain crossing designs SV RTL Coding Mobile Multimedia post-Si debug TCL language AHB RTL to GDS flow ISP knowledge Spyglass Lint unit level test plan Axi waiver creation BUS Protocols CDC checks PD teams Cadence LEC VHDL NOC designs Camera design formal verification digital front end design Documentation Skills low power design methodology Dft Dsp Verilog Perl

2 days ago

Staff Engineer - DFT

Permanent Job

Noida ,

4-7 years

ASIC coverage analysis RTL lint tool Cadence Encounter Test DFT DRC rules spyglass test mode timing constraints definition simulating test vectors equivalence check ATPG ATPG tool Team Work Skills Transition delay test coverage analysis communication Synopsis TetraMax English Tk TetraMax Dft Scan Insertion Problem Solving Skills perl Shell

6 days ago

Senior Staff Engineer - DFT

Permanent Job

Bengaluru / Bangalore ,

4-12 years

ASIC coverage analysis RTL lint tool DFTMax Cadence Encounter Test DFT DRC rules spyglass test mode timing constraints definition simulating test vectors equivalence check ATPG ATPG tool Team Work Skills Transition delay test coverage analysis communication Synopsis TetraMax English Tk TetraMax Dft Scan Insertion Problem Solving Skills perl Shell

2 days ago

RTL Design Engineer GPU

Permanent Job

Bengaluru / Bangalore ,

2-4 years

ASIC Synthesis primetime ASIC development AHB Rtl Design Memory controller designs Design Verification APB Axi reset Asynchronous interface LINT Design Compiler low power design Multi Clock designs Validation Timing Concepts System-Verilog cdc micro-architecture debug architecture AMBA protocols Verilog clocking Logic Design Microprocessors

6 days ago