Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design

Verilog, systemverilog, DDR memory controller calibration, Rtl Design, Logic analyzers, Calibration algorithms

Python Scripting, RTL design in Verilog SystemVerilog, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, PrimeTime or equivalent tools, C embedded experience, Circuit timing STA

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, FPGA design flow, Timing Closure, 5G LTE, Altera Agilex

Unix, Python, Shell, Linux, Skill, SoC Integration, Rtl Design

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes

Verilog, Uvm, Synopsys VCS, Cadence Incisive, VHDL, RTL design methodologies, Modelsim

Perl, Verilog, Python, SoC Verification, Makefiles, fuse floorsweep design, RTL Build flows, Padring, Design Automation, Rtl Design, Physical Design, Synthesis, Dft, System-On-Chip design implementation flow, SOC integration, Chip Design