Principal Design Engineer

Key Responsibilities

• Lead functional verification activities for DDR subsystem including memory controller and PHY IPs.
• Develop, enhance, and maintain SystemVerilog UVM-based verification environments.
• Create and execute test plans to ensure full functional and code coverage across all design configurations.
• Add new features and improve existing verification infrastructure to support evolving customer requirements.
• Validate customer configurations through regression testing and ensure robustness of IP delivery.
• Debug complex design issues using RTL (Verilog) and verification environments.
• Provide reference testbenches and standard test patterns for customer integration and validation.
• Track verification progress, identify risks, and implement mitigation strategies to ensure schedule adherence.
• Collaborate with cross-functional teams and customers for issue resolution and requirement alignment.
• Review verification deliverables and guide team members to maintain quality standards.
• Drive continuous improvement in verification methodologies and processes.
• Participate in technical discussions and represent verification team in internal and customer engagements.