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Job ID: 148088209
Skills:
Verilog, System Verilog, Functional Verification, LPDDR, Uvm, DDR memory protocols, HBM
Skills:
Unix Shell, System Verilog, Perl, Uvm, Gate Level Simulations, formal verification, NoCs, Design Verification, Automated flows, Interconnects
Skills:
regulators , Verilog, Matlab, IC design CAD tools, RF and Analog Design, Mixed signal circuits, TX, Bandgap bias circuits, RX, Spice, ADCs, Silicon Germanium SiGe BiCMOS, Spectre, Pll, DACs, HSIM, Filters, Bipolar Complementary Metal Oxide Semiconductor technology
Skills:
Static Timing Analysis, Python, Logic Design, Jasper, Perl, Tcl, Sta, IR drop, RTL implementation, post silicon validation, DFT concepts, Cadence Modus, Verification, Synthesis, ATPG tools, coverage analysis, Scan Insertion, RTL2GDS flow, Logic Synthesis, debugging skills, RTL lint tools, ATE debug, Logic Equivalent Checking, EDA Tools
Skills:
Area, PPA Performance, Micro-architecture, Timing, LPDDR6, Rtl Design, JEDEC specifications, DDR Controller
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